Multivalued Arithmetic Logic

It was established for a long time that the binary logic system is the standard system for Von-Neumann computation due to its hardware efficiency. With the rise of emerging devices, new computing paradigms, and new applications, it is necessary to re-evaluate multivalued logic systems and find the optimal system for each application. Hence, In this project, we aim to revisit the multivalued logic systems under such advances and evaluate the computational and hardware costs.

Related Publications:

Journals:

• M. Hout, M. E. Fouda, R. Kanj, and A. M. Eltawil, “In-memory Multi-valued Associative Processor” arXiv preprint, arXiv:2110.09643.
• R. Mohammed, M E. Fouda, I. Alouani, L. Said, A. Radwan, “Ternary Address Decoder Design", IJCTA, 2022.
• A. Mohammaden, M E. Fouda, I. Alouani, L. Said, A. Radwan, “CNTFET-based Ternary Multiply-and-Accumulate Unit", Electronics, 2022.
• A. Mohammaden, M E. Fouda, I. Alouani, L. Said, A. Radwan, “CNTFET Design of a Multiple-Port Ternary Register File", Microelectronics Journal, 2021.
• Nancy Soliman, M E. Fouda, A. Alhurbi, L. Said, A. Madian and A. Radwan, “Ternary Functions Implmentation using Memristive Thershold Logic'', IEEE ACCESS, 2019.
• Nancy Soliman, M E. Fouda, and A. G. Radwan “Memristor-CNTFET based ternary logic gates", Microelectronics Journal, 2018.

Conferences:

• D. Abdelrahman, R. Mohammed, M E. Fouda, L. Said and A. G. Radwan, “Comparative Study of CNTFET Implementations of 1-Trit Multiplier", IEEE Int. conf. of Microelectronics, 2020.
• A. Mohammaden, M E. Fouda, L. Said, A. Radwan, “Memristor-CNTFET based Ternary Full Adders", IEEE Int. Midwest Symposium on Circuits and Systems, 2020.
• N. Soliman, M E. Fouda, LA Said, AG Alharbi, AH Madian, AG Radwan, “CAD Tool for Two-Digit Ternary Functions Design" IEEE Int. conf. of Microelectronics 2019.